Updated CPU architecture

As you can see above, I've modified the CPU architecture slightly after giving some further thought to the design of the register file. Notice that the "C" register bus only exists between the ALU and the register file now, whereas before it went to all modules. Also notice that the A and B register buses are now bidirectional.

My thinking with the original design was that by predefining the function of each register bus (read/write) it would make the resulting circuitry simpler in the register file. But after further consideration, I realized that the most effective and efficient way to build the register file is to have each register be its own private board, with hooks into all three register buses.

In the new design, each register will be identical in circuitry, and a DIP switch will be used to identify it to the bus. So register W will have DIPs set to 00, X to 01, Y to 10, and Z to 11. That way I can take advantage of economies of scale -- I design and build one register unit, and then simply duplicate that unit 3 more times (not too bad if I'm printing PCBs). By focusing on the design of a single register, the overall design of the register file gets much simpler, even though the individual registers are more complex (for example, tristate buffers will need to be setup to properly address the buses depending on whether that register is selected on that bus). But the upsides are many. For one, I can build one register to start, and use it to test various aspects of the other units, before the other registers are complete. Using the DIP switches, I can simulate a register behaving like any of the four registers. Finally, it simplifies the cabling between the various units, since a single 40-pin cable can now carry all of the register traffic for all but the ALU. And the ALU will have one extra link to the register file. The register file itself will be a stack of four boards, all connected in parallel on the A, B, and C register buses.