System Architecture

Drew up the system architecture. The modules (gray units) are individually selected by the first two bits of the instruction. That way I can isolate each board for different types of instructions. Each board will have five bits of "instruction" to work with. The wide buses will be implemented using 40-pin rounded IDE cables (32 bits + 8 bits of control) .

The register file is where everything happens -- all of the instruction-processing units select one or two registers to read, the contents of which will be presented on the "blue" bus. They can also select a third register to write -- this can be the one of the registers being read. Registers/RAM are written on the rising clock edge.

The program counter presents the current instruction to all of the processing modules. It has a single feedback link to the jump/shift unit, which is capable of writing a new 15-bit address into the counting register. The program counter commits data and presents a new instruction on the falling clock edge.